1. Field of the Invention
The present invention relates to a multilevel programming method for a semiconductor storage, in particular, for floating gate nonvolatile semiconductor storage of a virtual ground memory array.
2. Description of the Prior Art
In recent years, virtual ground type flash memory devices aiming for high packing density have drawn attention, such as for example, `A New Cell Structure for Sub-quarter Micron High Density Flash Memory` (IEDM Technical Digest, pp.269-270, 1995), and an ACT (Asymmetrical Contactless Transistor) type flash memory disclosed in `An investigation of a sensing method of an ACT type flash memory` (ICD97-21, p.37, 1997, a technical report of The Institute of Electronics, Information and Communication Engineers).
In such an ACT type flash memory, programming (writing) and erasing operations are implemented based on the FN tunnel effect, and it is expected that it will be used for data storage.
Referring now to FIGS. 1 and 2, this ACT type flash memory will be described.
An ACT type flash memory uses the FN tunnel effect when programming and erasing as stated above, and has a virtual ground array configuration in which each bit line is shared between two memory cells. In such an ACT type flash memory, the bit lines are shared and formed of a diffusion layer to thereby reduce the number of contacts and enable a remarkable reduction of the array area, which leads to high integration.
Next, an ACT type flash memory device, as sectionally shown in FIGS. 2A and 2B, has, in order from the top, a control gate WL, an inter-layer insulating layer, a floating gate FG and a bit line (diffusion layer) arranged in a layered manner. The common bit line formed under and between the adjacent floating gates FG has different donor densities between the drain and source sides.
In FIG. 1 where ACT type flash memory cells are arranged in an arrayed configuration, MBLX represents a main bit line, SBLx represent a sub-bit line formed of a diffusion layer, WLx represents a word line, SGx represents a select gate selection signal line, CONTACT represents a contact point between a main bit line and a sub-bit line (belonging to different layers). Here, x represents an integer ranging from 0 to n.
Next, programming and erasing operations for an ACT type flash memory using the FN tunnel effect will be described.
First, programming the ACT type flash memory (see FIG. 2A) is performed with a negative voltage of -8 (v) applied to the control gate i.e., word line WL and a positive voltage of 5 (v) applied to the drain side. By this voltage application, the FN tunnel effect occurs on the drain side so that electrons are extracted from floating gate FG to the drain side. This extraction lowers the threshold voltage, thus implementing programming. Here, word line WL is also referred to as control gate WL.
An erase operation is performed with a high voltage of 10 (v) applied to control gate WL and a negative voltage of -8 (v) applied to a bit line BL and the substrate 109 (P-portion) so as to generate the FN tunnel effect between the channel layer (channel) and floating gate FG to thereby inject electrons into the floating gate FG. This injection of electrons raises the threshold voltage, which means that erasing is implemented.
A more detailed operation will be described based on the basic configuration of one memory cell M schematically shown in FIG. 3.
To begin with, for a program operation, or to extract electrons from floating gate FG, a negative voltage Vnw (-8 (v)) is applied to control gate WL, a positive voltage Vpp (+5 (v)) is applied to drain 105 and source 107 is set floating. Under these conditions, electrons are drawn from floating gate FG by the FN tunnel effect, and thereby the threshold voltage of memory cell M is lowered to about 1.5 (v).
For an erase operation, or to inject electrons into floating gate FG, a positive voltage Vpe (+10 (v)) is applied to control gate WL, a negative voltage Vns (-8 (v)) is applied to source 107 and drain 105 is set floating. Under these conditions electrons are injected into floating gate FG by the FN tunnel effect and thereby the threshold voltage of memory cell M is raised over about 4 (v).
A flash memory as above which uses the FN tunnel effect for both program and erase operations is called an FN-FN operating flash memory.
For a read operation, 3 (v) is applied to control gate WL, 1 (v) is applied to drain 105, 0 (v) is applied to source 107. The current flowing through cell M under the conditions, is detected by an unillustrated sensing circuit to read out the data.
The application of voltage for the above operations is summarized in Table 1.
TABLE 1 Application of voltage to a conventional flash memory Control Gate Drain Source P-type Well Program -8 V 5 V Open 0 V Erase 10 V Open -8 V -8 V Read 3 V 1 V 0 V 0 V
Here, the values shown in Table 1 are voltages to be applied to a selected memory cell M.
In the field of memory technology, as an attempt to aim at higher integration, multilevel techniques for introducing three or more threshold levels to each memory cell M have been published.
The examples include the methods disclosed in 1996 ISSCC Dig. Tech. Papers, pp36-37 "A 98 mm.sup.2 3.3V 64 Mb-Flash Memory with FN-NOR Type-4level cell" and in Japanese Patent Application Laid-Open Hei 6 No.177397.
In these methods, an FN-NOR type flash memory is used. Programming pulses for data `11`, `10` and `01` are simultaneously applied by applying different voltages to drains 105 with respect to each data, making use of the cell characteristics shown in FIG. 4. Based on these characteristics, memory cell M is programmed so as to have a voltage falling within one of the threshold voltages in the distribution shown in FIG. 5.
As shown in FIG. 5, data `00` is the erased state.
Subsequently, a verify operation (data verification after programming) is performed in two stages.
At the first stage, the reference voltage Ref (the standard voltage with which comparison is made) is set at around 2.3 (v), for example, so as to judge whether the threshold voltage falls within the `11` and `10` states or within the `01` and `00` states shown in FIG. 5.
Next, at the second stage, a different operation as follows will be effected based on the sensed result from the first stage.
When the sensed result from the first stage falls within the `11` or `10` state, then the reference voltage Ref is set at 1.3 (v), for example, so as to determine whether the level is `11` or `10`.
When the sensed result from the first stage falls within the `01` or `00` state, then the reference voltage Ref is set at around 3.3 (v), for example, so as to determine whether the level is `01` or `00`.
The above operations, that is, application of the programming pulses are repeated based on the verification result until the desired threshold voltage is obtained. Generally, the characteristics fluctuate when the FN tunnel effect is used, so that a pulse width shorter than that meeting the actual characteristic is used. That is, pulse applications (voltage application to drain 105) are stopped in the order in which programming is completed, so as to set the designated threshold voltages whilst preventing the lowering of the threshold voltages.
Next, description will be made of a case where the four-level programming method used in the aforementioned FN-NOR type flash memory is applied to a virtual ground ACT type flash memory.
FIG. 6 shows a flowchart of the programming algorithm of this case.
With the selected word line (WL) set at -8 (v), pulses of voltage corresponding to the data for individual cells M which are to be programmed with data `11`, `10` or `01` are applied simultaneously to respective drains 105 of the cells M as the drain voltage (Vd) so as to effect data writing (Step S11).
As the drain voltage Vd, 6 (v) is applied to the drains of cells M which are to be programmed with data `11`; 5 (v) is applied to the drains of cells M corresponding to data `10`; and 4 (v) is applied to the drains of cells M corresponding to data `01`. Here, data `00` corresponds to the erased state.
Subsequently, a verify operation (data verification after data writing) is performed (Step S12). For the verify operation, the word line (WL) is set at 1 (v), 2 (v) and 3 (v) as the reference voltage Ref, and it is judged whether the threshold voltage in each cell M is equal to or lower than the threshold level corresponding to the desired data.
Then, the cells M not having the desired levels are re-programmed (S11) and verified again (S12) so that they will have the desired levels (S13).
As a result, the distributions of the threshold levels under the condition in which there is no influence from the virtual ground array configuration are as follows: cells M programmed with data `11` have a threshold voltage ranging from 0.6 (v) to 1 (v); cells M programmed with data `10` have a threshold voltage ranging from 1.6 (v) to 2 (v); cells M programmed with data `01` have a threshold voltage ranging from 2.6 (v) to 3 (v). Data `00` corresponds to the erased state and hence has a voltage equal to 3.6 (v) or above.
However, the characteristics of programming using the FN tunnel effect fluctuate. Therefore, all the programmings of data `11`, `10` and `01` will not complete at the same time when using the aforementioned technique of switching the drain voltage Vd of FN-NOR type.
Further, when the aforementioned programming algorithm (FIG. 6) is applied to a virtual ground type array shown in FIG. 8, in addition to the fluctuation of the programming characteristics, apparent levels of the threshold voltages read out from memory cells M may shift higher or lower and hence the distribution may spread depending upon the pattern of data (the pattern of the threshold levels in the memory cells M) which has been programmed in the memory cells M. The spread of each threshold voltage reduces the detecting margin relative to the corresponding reference voltage Ref. leading to mal-detection.
Now, this widening behavior of the threshold voltage will be illustrated with reference to FIGS. 9, 10 and 11.
To begin with, a pattern of data which will not be affected by the virtual ground configuration is shown in FIG. 9.
As shown in FIG. 9, memory cells MO0, MO1, MO3, MO4 and MO5 are programmed with data `00` while memory cell MO2 is programmed with data `01`. The algorithm of programming in this case is as shown in FIG. 6.
Application of programming pulses is performed such that first, word line (WL0) set at -8 (v) and bit lines BL0, BL1, BL3, BL4 and BL5 are set open while 4 (v) is applied to bit line BL2 (c.f. FIG. 4, for programming of data `01`). This allows programming of memory cell MO2 (S11) so that the threshold voltage of memory cell MO2 lowers.
Next, a verify operation is performed (S12). Here, description will be made only about the verification of memory cell MO2.
Since data `01` corresponds to a threshold voltage equal to 3 (v) or below, word line (WL0) is set at 3 (v), and voltages shown in FIG. 9 are applied to corresponding bit lines BL.
That is, BL0=0 (v), BL1=1 (v), BL2=1 (v), BL3=0 (v), BL4=0 (v), BL5=1 (v) and BL6=1 (v).
Here, bit line BL1 is set at 1 (v) in order to prevent a roundabout current flowing through memory cell MO1. Here, it should be understood that the bit lines are provided as units of four bits (BL0 to BL3, BL4 to BL7 and the like), without a description in detail.
For verification, 1 (v) is applied to bit line BL2. In this case, if the current at the node on bit line BL2, flowing through memory cell MO2 from bit line BL2 to bit line BL3 (IO1 in FIG. 9) is greater than the sensitivity of an unillustrated sensing circuit (e.g., 1 (.mu.A) or greater), the writing is ended. If the current is lower than the sensitivity, application of the programming pulses to memory cell MO2 is repeated (see FIG. 6).
In the example shown in FIG. 9, since the cells other than memory cell MO2 are all in the erased state (having data `00` and hence having a high threshold, equal to or higher than 3.6 (v)), no current will flow out from bit line BL2 and no current will flow into bit line BL3 via neighboring cells. Therefore, for readout at the time of verification, no apparent change in threshold voltage due to the influence of the virtual ground type array configuration will appear.
Next, description will be made of cases where the virtual ground type array configuration has an influence on the result.
First, referring to FIG. 10, a case where the threshold voltage of memory cell M is seemingly lowered.
This is the case when memory cells MO0 and MO1 are programmed with data `11`, memory cell MO2 is programmed with `01` and memory cells MO3, MO4 and MO5 are programmed with `00`.
In this case, with word line (WL0) set at -8 (v), 6 (v) is applied to bit lines BL0 and BL1 (to write data `11` thereinto, c.f. FIG. 4) and 4 (v) is applied to bit line BL2 (to write data `01` thereinto) while bit lines BL3, BL4, BL5 and BL6 are set in the open state.
Because of fluctuations of the characteristics of individual memory cells M, the first pulse application for programming may produce a state where the memory cell corresponding to data `01` can be set at a desired level or below 3 (v) while memory cells MO0 and MO1 have been little varied, remaining at a voltage greater than 3.6 (v) (the aimed threshold voltage is 1 (v)).
If readout is performed in this state, the data pattern will be the same as that previously shown in FIG. 9.
That is, at this stage, when readout is performed with word line (WL0) set at 3.4 (v), the current measured at the node on bit line BL2, or the current IO1 flowing through memory cell MO2 from bit line BL2 to bit line BL3 is assumed as the normal current IO1 or is not be affected by the threshold levels of other memory cells (readout is performed with each readout voltage set higher by about 0.4 (v) than the corresponding threshold voltage while the verify voltage is set equal to the desired threshold voltage to be programmed unless otherwise specified.).
Thus, memory cell MO2 has been programmed with the desired value (corresponding to data `01`), the next programming pulse application is done with bit line BL2 open so that the threshold voltage of memory cell MO2 will not vary.
On the other hand, memory cells MO0 and MO1 have not reached the desired level (1 (v)), so that 6 (v) is applied to bit lines BL0 and BL1 for the next programming pulse application. Thus, application of some or several pulses is performed until memory cells MO0 and MO1 are set at a threshold voltage equal to or lower than the desired level, i.e., 1 (v), to complete the programming.
When readout is performed after the completion of programming, about 3.4 (v) which corresponds to the readout voltage D3 shown in FIG. 7 is applied to the word line (WL0) in order to distinguish data `00` from data `01`, for example.
When data is read out from memory cell MO2, a roundabout current Ir flows via memory cells MO0 and MO1 having lower thresholds, In addition to the normal current IO1, making up the current .vertline.b.vertline. at the node on bit line BL2, as shown in FIG. 10.
As a result, the current .vertline.b.vertline. measured at the node on bit line BL2 is increased and detected as current (IO1+Ir). Therefore, the threshold voltage of memory cells MO2 is seemingly shifted in the lower direction.
Up to here was the description of the case where the threshold voltage is shifted in the lower direction.
Next, referring to FIG. 11, a case where the threshold voltage is shifted in the higher direction will be discussed. This case corresponds to a case, for example, where memory cells MO0, MO1 and MO5 are programmed with `00`, memory cell MO2 are programmed with `01` and memory cells MO3 and MO4 are programmed with `11`. In this case, programming pulse application is performed with word line WL0 set at -8 (v), 4 (v) is applied as drain voltage Vd to bit line BL2, and 6 (v) is applied as drain voltage Vd to bit lines BL3 and BL4 while bit lines BL0, BL1 and BL5 are set in the open state. The characteristics of individual memory cells M vary as stated above: for example, the first pulse application may produce a state where the threshold voltage of memory cells MO2 is set at a level equal to or below 3 (v) while the threshold voltages of memory cells MO3 and MO4 have been little varied, remaining at a voltage greater than 4 (v).
If readout is performed in this state, the pattern of data is the same as that previously shown in FIG. 9. Accordingly, the current measured at the node on bit line BL2, i.e., the current flowing through memory cell MO2 from bit line BL2 to BL3 is assumed as the normal current IO1.
Thereby, programming of memory cell MO2 has been completed. So the next programming pulse application is done with bit line BL2 open while a drain voltage of 6 (v) is applied to bit lines BL3 and BL4. Thus, programming pulse application and verification are repeated for some or several times. By this procedure, the threshold voltages of memory cells MO3 and MO4 are reduced to the desired level, i.e., 1 (v) or below.
After the completion of the entire programming, when data is read out from memory cell MO2 with word line WL0 set at 3.4 (v), a roundabout current Ij flows via memory cells MO3 and MO4 having lower thresholds (1(v)), from bit line BL5 to BL3 as shown in FIG. 11, resultantly raising the potential of bit line BL3.
Thereby, a current (IO1-Ia) (here Ia is the reduction in current due to the influence of roundabout current Ij from memory cells MO3 and MO4 as shown in FIG. 11) flows at the node on bit line BL2 from bit line BL2 to BL3 via memory cell MO2. Therefore, the current detected at the node on bit line BL2 is reduced by (-Ia) compared to the prior state before the data in memory cells MO3 and MO4 are established. Accordingly, the threshold voltage of memory cell MO2 is seemingly detected to be higher and hence is observed that the threshold level is shifted higher.
The hatched area in FIG. 12 represents the widened distribution of the threshold voltage of the memory cell M which has been programmed with data `01`.
A further description in detail will be made about roundabout currents Ir and Ij which cause the threshold voltage distribution to spread.
First, description will be made of roundabout current Ir.
As shown in FIG. 10, in the case where memory cells MO0 and MO1 have a low threshold voltage such as for representing data `11`, a roundabout current Ir will flow by way of memory cells MO0 and MO1 in addition to the current IO1 normally flowing through memory cell MO2 when data is read out from memory cell MO2.
Because bit line BL1 is also set at 1 V in order to prevent the occurrence of roundabout current, normally no roundabout current should occur. However, a virtual ground ACT type flash memory uses bit lines BL formed of a diffusion layer as shown in FIGS. 1 and 2, so that it presents high resistance, which may cause a voltage drop of about 0.5 (v), for example. This is why a roundabout current Ir as above will arise.
In this way, if an increased current (IO1+Ir), which is greater than the normal current IO1, is detected at the node on bit line BL2. the threshold voltage of cell MO2 is erroneously detected as a seemingly lower value by an unillustrated sensing circuit. This state means that the distribution of the threshold level is seemingly shifted towards the lower side (in the direction of arrow L in FIG. 12) widening its range, as shown in FIG. 12.
Further, also when cells MO0 and MO1 have data `00` (which has a greater threshold voltage than that of cell 02) and cells MO3 and MO4 have data `11` (which has a lower threshold voltage than that of cell 02) as shown in FIG. 11, erroneous detection can occur. In this case, no roundabout current Ir flows on the cell MO1 side. However, because bit line BL5 is set at 1 (v) (the same pattern of voltage applied to BL1 in the block of bit lines BL0 to BL3 is applied correspondingly to BL5 in the block of bit lines BL4 to BL7), a roundabout current Ij flows through memory cells MO3 and MO4 having lower threshold voltages. Theoretically if bit line BL4 is set at 0 (v), a current only flows through bit line BL4 by way of memory cell MO4 without producing any influence on bit line BL3. However, since bit lines are formed of a diffusion layer having a high resistivity as stated above, the potential of bit line BL4 arises and hence a current also flows via memory cell MO3. Since bit line BL3 is also formed of a diffusion layer, the potential also rises over the inherent potential or 0 (v).
In the above case, the current (.vertline.b.vertline.=IO1-Ia:Ia is the current reduction in response to the increase of the potential of bit line BL3 due to roundabout current IJ) for cell MO2 at the node of bit line BL2 decreases due to the backgating effect. This causes the apparent threshold voltage to be detected higher than that in the normal state of memory cell MO2 (in the state where only current IO1 flows therethrough).
This state means that the detected distribution of the apparent threshold level is widened in the direction of arrow H as indicated by the hatched area in FIG. 12.
As above, the virtual ground array configuration will affect and widen the distribution of the threshold voltage as shown in FIG. 12 and disturb correct readout when data is read out after the completion of programming.
As shown in FIG. 12, if there is no influence of roundabout current from the virtual ground array configuration, the distribution of the threshold level corresponding to data `01` should normally fall within the range of 2.6 to 3.0 (v), but the distribution will spread falling within the range of 2.3 to 3.2 (v) due to that influence. Therefore, if the readout voltage D2 (see FIG. 7) for distinguishing between data `01` and `10` is set at 2.4 (v), data will be read out erroneously.